A buck switching mode power supply is a type of DC-DC converter commonly used in electronic devices to efficiently step down voltage levels. It operates on the principle of rapidly switching a semiconductor switch (usually a transistor) to control the energy flow from the input to the output. By doing so, a buck converter reduces the voltage while increasing the current, enabling the delivery of a stable, lower-voltage output to power electronic components. Buck converters are valued for their high efficiency, compact size, and versatility, making them essential in various applications such as power supplies for electronics, battery chargers, and LED drivers.

For this project we had the following constraints per instructor
1) Build a voltage regulator
2) Design a circuit that senses an input voltage Vin. (this input is connected to the output voltage of the power supply, Vout, for feedback and control). Your design should use the bandgap from part 1. The output (called Enable) of the circuit is a logic 1 (vdd) when Vin is greater than 3.125 V and a logic 0 (ground) when Vin is less than 3.125 V. The circuit’s input, Vin, should draw no more than 50 uA of current and no less than 10 uA of current. A practical design concern pops–up when Vin is near 3.125 V, which it will be in these projects. What will happen, if the circuit isn't designed correctly, is that the signal Enable will oscillate since Vin is moving slightly above and below 3.125 V. To avoid these oscillations, design your circuit with a small amount of hysteresis.

3) Use your design from part 2, that is, using Enable, to drive buffers (inverters) that enable/disable a PMOS switch connected between VDD and cell's output, out, and an NMOS switch connected between the cell's output, out, and ground. Your report, among other items, should discuss your thoughts on device sizing. Ensure the buffer you design has a lock–out feature.

4) The CMOS synchronous Buck switching power supply you are designing will be connected in 4 places: VDD, gnd, out, and Vout. What you LVS and DRC will be this cell; however, you will need to simulate this cell (generate a symbol view of your final design having 4 pins, or 2 pins if using global vdd! and gnd!) with the off–chip inductor and capacitor (the inductor and capacitor are not part of what we send out for fabrication). The output of your design, out, is connected to the inductor. The other side of the inductor is connected to Vout (the inductor is connected between out and Vout). The capacitor is connected from Vout to ground. Your report should detail your selection of the inductor and capacitor along with simulation results showing performance with varying temperature and power supply (plot your design's efficiency vs load current with different temperatures and power supply voltages). Of course, again, you need to also provide the details indicated above. Note that efficiency, E, can be calculated using E = (Vout * Iload)/(VDD * AVG(I(VDD))) where AVG(I(VDD)) is the average current flowing the power supply, VDD.