Design Objectives and Overview

The primary goal of this project is to design and analyze an 8-path continuous-time delta-sigma analog-to-digital converter (ΔΣ ADC) using a modified KD1S topology. The design must eliminate switched-capacitor circuits and non-overlapping clock signals, relying instead on a continuous-time implementation. The objectives include achieving performance comparable to the design in Fig. 9.32 of CMOS Mixed-Signal Circuit Design while optimizing power consumption, signal-to-noise ratio (SNR), bandwidth (BW), and effective number of bits (Neff).